This invention relates to a semiconductor device comprising a field effect device having a gate structure.
In particular, the present invention relates to a semiconductor device comprising a semiconductor body comprising a field effect device wherein the semiconductor body has source and drain regions spaced apart by a body region, a source electrode contacts the source region and a drain electrode contacts the drain region, and a gate structure is provided for controlling a conduction channel in a conduction channel accommodation portion of the body region extending between the source and drain regions.
U.S. Pat. No. 4,835,584 describes a field effect transistor in which the source, gate structure and drain are formed within a trench in a semiconductor substrate. In this transistor, the gate width (where, as is understood in the art, the gate width is the dimension perpendicular to the flow of current through a conduction channel controlled by the gate, and the gate length is the dimension parallel to the flow of current through the conduction channel) is determined by the depth of the trench and can be increased substantially without increasing the surface area occupied by the transistor. This enables a transistor having a good conduction channel length to width ratio and so a low on-resistance (Rdson), good current handling capabilities and gain to be provided. However, increasing the trench depth for a given trench area (so as to increase the gate width) increases the aspect ratio and makes it more difficult to deposit metallisation to form the source and drain electrodes and may lead to increased source and drain resistance.
It is an aim of the present invention to provide a semiconductor device comprising a field effect device that overcomes or at least mitigates the abovementioned problems.
Advantageous technical features in accordance with the present invention are set out in the appended claims.
In one aspect, the present invention provides a semiconductor device comprising a semiconductor body comprising a field effect device, the semiconductor body having source and drain regions spaced apart by a body region, the field effect device having within a trench (having end, side and bottom walls) a gate structure for controlling a conduction channel in a conduction channel accommodation portion of the body region between the source and drain regions, wherein the field effect device is provided as a mesa structure having end and side walls, the source and drain regions meet respective end walls of the mesa structure, a source electrode contacts the source region and a drain electrode contacts the drain region, and the conduction channel accommodation portion extends between the source and drain regions and along one trench side wall, along the trench bottom wall and along the other trench side wall.
In another aspect, the present invention provides a semiconductor device comprising a semiconductor body comprising a field effect device, the semiconductor body having source and drain regions spaced apart by a body region, the field effect device having a gate structure for controlling a conduction channel in a conduction channel accommodation portion of the body region between the source and drain regions, wherein the field effect device is provided as a mesa structure having end and side walls and a top, the source and drain regions meet respective end walls of the mesa structure and are separated by a portion of the mesa structure forming the body region and meeting the top and the side walls of the mesa structure, a source electrode contacting the source region, and a drain electrode contacting the drain region, and the gate structure extends on the surfaces of the body region so that the conduction channel accommodation portion extends along one side wall, the top and the other side wall.
In yet another aspect, the present invention provides a field effect device formed as a mesa structure with source and drain regions at opposite ends of a trench formed in the mesa structure, a gate structure provided within the trench to control a conduction channel between the source and drain regions, and source and drain electrodes contacting respective parts of the source and drain regions that meet end and/or side walls of the mesa structure so that the source and drain electrodes extend partly along the end and/or side walls of the mesa structure. A series of alternating source and drain regions may be provided along the length of the mesa structure. In this case, the respective field effect devices may be connected in parallel to provide a higher power, parallel cell device. Thus, conductive connections outside the mesa may respectively connect the source regions in parallel and the drain regions in parallel.
Providing the field effect device as a mesa structure with the source and drain electrodes contacting portions of the source and drain regions exposed at walls of the mesa structure enables the mesa structure to be relatively deep, while still achieving good contact to the source and drain regions. This allows a large increase in gate width enabling a low on-resistance (Rdson) and good current carrying capabilities and gain to be achieved, without detrimentally increasing source or drain resistance. A compact device structure can be achieved by providing the gate structure in a trench that has side walls parallel to the side walls of the mesa structure.
When the gate structure is provided within a trench in the mesa structure, the present invention readily permits the side walls of the mesa structure (with source and drain regions) that are contacted by the source and drain electrodes to be deeper than the side walls of the trench (and so deeper than the depth of the conduction channel controlled by the gate). This depth relation of trench and mesa structure permits a more uniform current flow from the conduction channel to the source and drain regions and their electrodes, and so reduces the spreading resistance. As a result an even lower on-resistance (Rdson) is possible when this depth relationship is adopted in accordance with the invention.
The total semiconductor device may comprise a plurality of the mesa structures located side-by-side, with the field effect devices of the respective mesa structures connected in parallel to provide a higher power, parallel cell device.